`include "ascon_define.v"

module `ONE_CYC
    #(
     parameter DAT_W                             = 1
     )
     (
     input                                       clk_i,
     input                                       rst_n_i,
     input                           [DAT_W-1:0] dat_d_i,

     output                          [DAT_W-1:0] dat_q_o
     );

wire                                 [DAT_W-1:0] dat_d_w;
reg                                  [DAT_W-1:0] dat_q_r;


assign dat_d_w          = dat_d_i;

assign dat_q_o          = dat_q_r;

always @(posedge clk_i or negedge rst_n_i)
begin : DAT_Q_R_PROG
  if (rst_n_i == 1'b0)
    dat_q_r             <= {DAT_W{1'b0}};
  else
    dat_q_r             <= dat_d_w;
end

endmodule